Chopper stabilized comparator for successive approximation register analog to digital converter

ABSTRACT

The disclosure includes an analog to digital converter (ADC). The ADC includes a comparator to compare sample values of an analog signal in an analog domain to reference values to determine digital values in a digital domain. The digital values correspond to the analog signal and may be determined according to successive approximation. The ADC also includes chop switches to modulate the analog signal to increase a frequency of flicker noise in the analog domain. The ADC also includes an un-chop switch to demodulate the digital values in the digital domain prior filtration of the flicker noise by a digital filter.

CROSS-REFERENCES TO RELATED APPLICATIONS

The present application claims benefit from U.S. Provisional PatentApplication Ser. No. 62/438,922, filed Dec. 23, 2016, and entitled“Audio Successive Approximation Register ADC Having Chopper StabilizedComparator,” which is incorporated herein by reference as if reproducedin its entirety.

BACKGROUND

Flicker noise is potentially a problem when operating any electroniccomponent at low frequencies. Complementary Metal Oxide Semiconductor(CMOS) based devices may experience particularly high flicker noise.Flicker noise may occur when electrons become temporarily trapped inimperfections in a conductive material. Such trapped electrons may movethrough the conductor in a random walk pattern that is unpredictable,which results in unpredictable noise. Flicker noise can be describedmathematically as occurring as an inverse of a signal frequency. Assuch, flicker noise is sometimes referred to as 1/f noise, where f is acorresponding signal frequency. Accordingly, flicker noise becomes atrivial concern at high frequencies. However, flicker noise can dominateother noise mechanisms when operating at low frequencies. For example,flicker noise may be a significant concern when operating CMOS basedanalog to digital converters (ADCs). Flicker noise may be an evengreater concern when such an ADC is employed to convert audio signals,as such audio signals occur at low frequencies (e.g. approximatelytwenty hertz (Hz) to approximately twenty kilohertz (kHz). Flicker noisein CMOS is related to the size of the gate area, and can be reduces byincreasing the size of the device. However, increasing gate size solelyto decrease flicker noise is impractical as smaller device sizes aregenerally preferred in CMOS designs.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects, features and advantages of embodiments of the presentdisclosure will become apparent from the following description ofembodiments in reference to the appended drawings in which:

FIG. 1 is a schematic diagram of an example Successive ApproximationRegister (SAR) ADC architecture.

FIG. 2 is a schematic diagram of an example SAR ADC with a chopperstabilized comparator.

FIG. 3 is a schematic diagram of another example SAR ADC with a chopperstabilized comparator.

FIG. 4 is a schematic diagram of an example digital signal processor(DSP) to remove modulated flicker noise.

FIG. 5 is a flowchart of an example method of operating a SAR ADC with achopper stabilized comparator.

DETAILED DESCRIPTION

Disclosed herein is a SAR ADC that employs both chopper switches and anun-chop switch. A SAR core sequencer may control both the chopperswitches and the un-chop switch. The chopper switches modulate thesignal to increase the frequency of the flicker noise to a frequencyoutside the band of interest (e.g. outside the audio band). A digitalsignal processor (DSP) may then filter the flicker noise out of thedigital signal, for example by employing a bandpass filter. For example,the chopper switches may invert an incoming analog signal in the analogdomain. A comparator may then be employed to convert the analog signalinto a digital signal according to a SAR process. The un-chop switch maythen be employed to invert the signal in the digital domain to correctfor the inversion in the analog domain (e.g. maintain consistentpolarity). In some embodiments, the chop switches may be positionedbetween a sampling capacitor array and the comparator. In anotherexample, the chop switches may be positioned at an input to the samplingcapacitor array. In another example, the un-chop switch may beimplemented in a SAR register. In yet another example, the un-chopswitch may be implemented between a correction circuit and the DSP.

FIG. 1 is a schematic diagram of an example SAR ADC 100 architecture.The SAR ADC 100 includes a capacitor array 110, a comparator 120, a SAR130, and a Digital to Analog Converter (DAC) 111 coupled as illustrated.The capacitor array 110 is coupled to an incoming analog signal 161. Thecapacitor array 110 includes a plurality of capacitors of varying levelsof capacitance. The capacitors store charge from the analog signal 161as a sample of the analog signal at a discrete instance in time. The SAR130 may include a register for storing digital data as well as a circuitfor providing known reference values. The DAC 111 is any device capableof converting a digital value to a corresponding analog signal value.The SAR 130 is configured to forward a known reference value (e.g. aone) via the DAC 111 to the comparator 120 for each bit of the sample.The comparator 120 is any electronic device capable of comparing twovoltages and outputting an indication of which voltage is larger. Thecomparator 120 receives both voltage from the sample in the capacitorarray 110 and the known value from the SAR 130 via the DAC 111. Thecomparator 120 then indicates which value is larger. The result of thecomparison is stored in the SAR 130 as a bit of a corresponding digitalvalue 162.

As such, the capacitor array 110 may include a capacitor/capacitor groupfor storing a portion of the analog signal for each bit desired in thedigital value 162. The SAR ADC 100 may then iteratively test theelectrical charge from each group of capacitors in the capacitor array110 against the known value from the SAR 130 on a bit by bit basis. Theresults are stored in the SAR 130. Once all the desired bits have beentested, the resulting digital value 162 may be forwarded from the SARADC 100 for further use by coupled systems, for example at a DSP. TheSAR ADC 100 provides accurate values so long as the capacitors in thecapacitor array 110 include an expected capacitance. However, due tomanufacturing variation, the capacitance of the capacitor array 110 mayvary significantly from device to device. As such, various calibrationtechniques are discussed below to account for such variation. Suchcalibration allows the SAR ADC 100 to employ significantly reducedprecision components, which in turn allows for the use of lower powercomponents while maintaining accuracy and hence maintaining high SNR.

While an SAR ADC 100 may be implemented in many different fashions, itshould be noted that the capacitor array 110 and the DAC 111 may beimplemented in a common capacitor network. Further, the comparator 120may contain one or more preamplifier stages that can be configured as asampling Operational Transconductance Amplifier (OTA). Further, thecomparator 120 can be configured as the only active component of theanalog circuitry of SAR ADC 100. This supports creation of a low powerand high precision design. While the reference accuracy of the DAC 111may limit the resolution the SAR ADC 100 can achieve, digitalcalibration can be employed to calibrate the capacitor array 110 andmitigate such concerns.

It should also be noted that the SAR ADC 100 architecture may beimplemented in CMOS. Further, when the analog signal 161 is an audiosignal, the SAR ADC 100 architecture may be employed for audioprocessing. In such a case, flicker noise may occur across thecomparator 120. As such, chop switches may be positioned on the analogside of the comparator to modulate the analog signal 161 andcorresponding flicker noise. This may increase the frequency of theflicker noise and place the flicker noise outside of the audio band.Hence, the flicker noise may be filtered out during digital processing.Un-chop switches may be placed on the digital side of the comparator120. The un-chop switches may selectively invert the bits of the digitalvalues 162 so that the digital values 162 maintain a consistent polaritydespite the chopping. Hence, the chopping and un-chopping may betransparent to the other signal components. As an example, the chopswitches may invert the analog signal 161 values before to the SAR ADC100 takes a sample at the capacitor array 110. The un-chop maysimultaneously invert the digital value 162 during the SAR process forthe sample. The chop switches and un-chop switches may then be invertedwhen another sample is taken for a next digital value 162. In somecases, the chopping/un-chopping polarity may only be switched between afew digital values 162 (e.g. every third value, every fourth value,etc.) as desired. This is because high frequency modulation may not berequired to place the flicker noise outside of the audio band (e.g. asthe audio band is relatively low frequency).

FIG. 2 is a schematic diagram of an example SAR ADC 200 with a chopperstabilized comparator 220, which may be employed to implement a SAR ADCarchitecture, such as SAR ADC 100 architecture. The SAR ADC 200 includesa capacitor array 210, a comparator 220, a SAR 230, and a DAC 211, whichmay be substantially similar to capacitor array 110, comparator 120, SAR130, and DAC 111, respectively. The SAR ADC 200 receives an analogsignal 261 and generates digital values 262, which are substantiallysimilar to the analog signal 161 and digital value 162, respectively.

The analog signal 261, may be any continuous electrical. In someexamples, the analog signal contains audio data in a frequency bandbetween about twenty Hz and about twenty kHz. As a specific example, theaudio signal 261 may audio recorded by one or more microphones during anactive noise cancellation process employed in a headphone set. Asanother specific example, the analog signal 261 may be an audio signalemployed as part of a BLUETOOTH speaker. The analog signal 261 may bereceived at the capacitor array 210. The capacitor array 210 includes asampling network 212 of capacitors to store sample values. For example,the analog signal 261 may charge the capacitors of the sampling networkduring a SAR ADC 200 sampling phase. At the end of the sampling phase,the analog signal 261 is disconnected from the sampling network 212. Assuch, at the end of the sampling phase, the sampling network 212 ofcapacitors contains an amount of charge corresponding to a value of theanalog signal 261 (e.g. which may be described in terms of amplitude,current, voltage, etc.) at a discrete instant in time. The SAR ADC 200may then enter a SAR phase to successively approximate the sample valuestored in the sampling network as a digital value 262. The SAR ADC 200may then return to a sample phase to obtain a next sample from theanalog signal 261, etc. The capacitor array 210 may also include the DAC210, which provides reference values from the SAR 230 that are employedto successively approximate the digital values 262.

The SAR ADC 200 also includes the comparator 220 to compare samplevalues of the analog signal 261 in an analog domain 281 to referencevalues from the DAC 211 to determine digital values 262 in a digitaldomain 282. Hence, the digital values 262 correspond to values of theanalog signal 261. Components operating on the input side of thecomparator 220 can be considered to operate according to analog signalprocessing principles and hence such components make up the analogdomain 281. Components operating on the output side of the comparator220 can be considered to operate according to digital signal processingprinciples and hence such components make up the digital domain 281. Theanalog domain 281 and the digital domain 282 are depicted as beingdivided by a dashed line. While the DAC 211 is depicted in the analogdomain 281 for visual simplicity, it should be noted that the DAC 211also acts as a dividing component between the analog domain 281 and thedigital domain 282.

The comparator 200 contains a preamplifier 221 and a latch 222. The apreamplifier 221 may be any electronic device that increases the powerof a weak electrical signal to create a signal of sufficient strengthfor further processing. The latch 222 is any circuit with two stablestates, which can be employed to store information. Specifically, thepreamplifier 221 amplifies a sample from the sampling network 212 aswell as a reference value from the SAR 230 via the DAC 211. Thecomparator 220 compares the two values and initiates the latch 222 tooutput an indication of which value is greater (or lesser depending onimplementation).

The SAR 230 stores digital value bits during determination of thedigital values 262. Specifically, the SAR 230 may store the results ofeach comparison by the comparator 220 as a bit in a register and providea reference value to be employed to determine a next bit. Once a desirednumber of bits have been tested and stored, an approximate digital value262 has been generated that corresponds to the analog signal 261 samplevalue obtained during the sampling phase. The SAR ADC 200 may thenreenter the sampling phase and obtain another sample value of the analogsignal at the sampling network.

As noted above, the digital values 262 stored in the SAR 230 may beapproximate. For example, capacitors may vary in capacitance due tovariations in manufacturing processes. As such, the capacitors in thesampling network 212 and/or the DAC 211 may be measured during acalibration process. For example, known input values may be forwarded tothe capacitor array 210 for testing purposes during a calibrationprocess (e.g. on startup, on system update, on command by user, etc.)The calibration process results in various capacitor weights that arestored in a correction circuit 250. The correction circuit 250 is acircuit configured to store the capacitor weights, for example in alookup table, and apply such weights to approximate digital values 262to arrive at final digital values 262. Hence, the correction circuit 250is configured to correct the digital values 262 based on samplingcapacitor weights. Once the weights have been applied, the digital value262 has been corrected for any capacitor variance in the capacitorarray.

The SAR ADC 200 also include a SAR core sequencer 240. The SAR core 240may be a control circuit configured to control the components of SAR ADC200 in order to enact sampling, successive approximation, and/orcalibration. For example, the SAR core sequencer 240 may manage a dutycycle for the SAR ADC 200 by sending command pulses to the SAR ADC 200components for clock cycles according to a finite state machine. The SARcore 240 may be implemented as any form of control processor, forexample as an Application Specific Integrated Circuit (ASIC), a FieldProgrammable Gate Array (FPGA), a Digital Signal Processor (DSP), ageneral purpose processor, and/or any other control circuit. The SARcore 240 is depicted as connecting to other components via a line withdots and dashes to indicate that such connects are for control purposesas opposed to solid lines for data processing (e.g. control plane vsdata plane).

As discussed above, flicker noise may occur in SAR ADC 200, for examplewhen SAR ADC 200 is implemented in CMOS and/or when SAR ADC 200 isemployed to convert audio data in an analog signal 261 into audio datain a corresponding digital signal including digital values 262.Accordingly, the SAR ADC 200 includes one or more chop switches 270 tomodulate the analog signal 261 to increase the frequency of the flickernoise in the analog domain 281. The SAR ADC 200 also includes an un-chopswitch 231 to demodulate the digital values 262 in the digital domain282.

The chop switches 270 may be implemented as a plurality of switches thatselectively invert the comparator 220 inputs based on commands from theSAR core sequencer 240. For example, the chop switches 270 may swap theoutput from the sampling network 212 and the output of the DAC 211between the positive and negative inputs, respectively, to thepreamplifier 221 of the comparator. This effectively inverts the bits ofthe digital value 262. In another example, the SAR ADC 200 may employdifferential signals where the sampling network 212 and the DAC eachtransmit a value by communicating a signal pair. In such a case, thechop switches 270 may swap the inputs by swapping the polarity of thedigital pairs. In either case, such swapping, which may be referred toas chopping, may also modulate the frequency noise. The more often thechop switches 270 swap the input, the high the frequency of themodulated flicker noise. The chop switches 270 may chop the analogsignal 261 samples at a rate sufficient to raise the frequency of theflicker noise outside of the frequency band of interest. For example,chop switches 270 may increase the frequency of the flicker noise to avalue outside of the audio band so that the flicker noise can befiltered out by a frequency specific filter, such as a bandpass filterset to the audio band. In SAR ADC 200, the chop switches 270 thatmodulate the analog signal 261 are coupled between an output of thecapacitor array 210 and an input to the comparator 220 as shown in FIG.2. The chop switches 270 may swap inputs before/after a sampling phaseis complete for each new sample, before/after every other samplingphase, before/after every third sampling phase, etc. The chop switches270 may remain in a constant position during the SAR phase to maintainconsistent polarity between successive bits. Chopping between each ADCconversion may result in a chopping frequency that is half of the ADCconversion rate. Chopping between an integer number of conversions mayresult in chopping frequency that is an integer division of the of theADC conversion rate. A lower integer division chopping frequency mayminimize artifacts produced by the chopping process, and may be employedso long as the resultant chopping frequency is sufficient to move theflicker noise out of the band of interest (e.g. the audio band). Forexample, the ADC conversion rate employed may be about 1.024 megahertz(MHz), and the corresponding chopping frequency employed may be 256 kHz.

The un-chop switch 231 may be implemented in the SAR 230. For example,the un-chop switch 231 may be implemented as a multiplexer coupled to aninput line 233 and an inverted line 231. The inverted line 232 maycontain the inverse of data on the input line 233. The un-chop switchmay demodulate the digital values 262 by switching an output between theinput line 233 and the inverted line 232. By selectively inverting thedigital values 262 when the chop switches 270 are swapped, the chopswitch 231 may ensure the digital values 262 maintain a consistentpolarity. Accordingly, the chopping and un-chopping may be performedtransparently to the other components, and the data in the digitalvalues 262 may not be affected. In other words, the un-chop switch 231in the digital domain 282 may correct for the inversion caused by thechop switches 270 in the analog domain. Further, the SAR core sequencer240 may control both the chop switches 270 and the un-chop switch 231.Hence, the SAR core sequencer may control the chop switches 270 and theun-chop switch 231 to align modulation in the analog domain 281 todemodulation in the digital domain 282 to maintain a consistent polarityof the digital values 262.

FIG. 3 is a schematic diagram of another example SAR ADC 300 with achopper stabilized comparator, which may be employed to implement a SARADC architecture, such as SAR ADC 100 architecture. SAR ADC 300 may besubstantially similar to SAR ADC 200, but employs chop switches 370 andan un-chop switch 331 at different locations. SAR ADC 300 includes chopswitches 370, a capacitor array 310 with a sampling network 312 and aDAC 311, a comparator 320 with a preamplifier 321 and a latch 322, a SARcore sequencer 340, a SAR 330, a correction circuit 350, and an un-chopswitch 331, which may be substantially similar to chop switches 270,capacitor array 210, sampling network 212, DAC 211, comparator 220,preamplifier 221, latch 222, SAR core sequencer 240, SAR 230, correctioncircuit 250, and un-chop switch 231, respectively. The SAR ADC 300converts an analog signal 361 in the analog domain 381 into digitalvalues 362 in a digital domain 382, which are similar to the analogsignal 261, the analog domain 281, the digital values 262, and thedigital domain 282, respectively. Further, the un-chop switch 331 iscoupled to an input line 333 and an inverted line 331, which aresubstantially similar to the input line 233 and the inverted line 231,respectively.

Unlike SAR ADC 200, the SAR ADC 300 chop switches 370 that modulate theanalog signal 361 are coupled to an input of the capacitor array 310.Hence, the chop switches 370 operate directly on the analog signal 361and/or the reference value from the DAC 311 instead of operating on theanalog signal 631 samples. Further, the un-chop switch 331 andassociated input line 333 and inverted line 332 are coupled to theoutput of the correction circuit 350. The SAR ADC 200 also includes aDSP to process the digital values, as discussed below. Accordingly, theun-chop switch 331 that demodulates the digital values 362 is coupledbetween the correction circuit 350 and the DSP. The chop switches 370and the un-chop switch 331 increase the frequency of flicker noise whilemaintaining a consistent digital value 362 polarity in a mannersubstantially similar to chop switches 270 and un-chop switch 231 asdescribed above with respect to FIG. 2. Also, SAR core sequencer 340 maycontrol the chop switches 370 and the un-chop switch 331 to maintainconsistent polarity as discussed above. For example, the SAR coresequencer 340 may transmit a chop clock signal to select between thetrue or negative (e.g. input line 333 and inverted line 331) of thecorrection circuit 350 output word.

FIG. 4 is a schematic diagram of an example digital signal processor(DSP) 400 to remove modulated flicker noise. A DSP 400 is a specializedmicroprocessor with an architecture optimized for digital signalprocessing. The DSP 400 may receive digital values 462 from an ADC coreor multiple parallel cores as part of a digital stream. As such, digitalvalues 462 may be substantially similar to digital values 162, 262,and/or 362. The digital values 462 may contain accurate digital valuescorresponding to analog signal samples. The digital values 462 may alsocontain flicker noise modulated by chopping as discussed above. Theflicker noise is has been modulated to a frequency in excess of thefrequency of interest. For example, the modulated flicker noise mayoccur at a higher frequency that is outside the audio band. As aspecific example, the modulated flicker noise may occur at a frequencyabove about twenty kHz. The DSP 400 may include digital filters 491 thatfilter the digital values 462 based on frequency. For example, thedigital filters 491 may include a bandpass filter with a low frequencybounds set to about twenty Hz and a high frequency bounds set to abouttwenty kHz. As such, the digital filters 491 may filter out the flickernoise without affecting the underlying data in the digital values 462.Accordingly, the ADC may include a DSP 400 to apply a digital filter 491to filter out the flicker noise by filtering out data associated withthe increased flicker noise frequency.

FIG. 5 is a flowchart of an example method 500 of operating a SAR ADCwith a chopper stabilized comparator, such as SAR ADC 200 and/or 300with a DSP 400. For example, the method 500 may be implemented by a SARcore sequencer, such as SAR core sequencer 240 and/or 340.

At block 501, a chop switch is employed to selectively alternate apolarity of samples of an analog signal to modulate flicker noise. Asnoted above, the polarity of sampled analog signal or the polarity ofthe analog signal prior to sampling may be alternated depending on theembodiment. Such polarity alternation may include swapping a connectionbetween the analog signal and a comparator with a connection between areference signal and the comparator, and vice versa. Such a polarityalteration may also be achieved in a differential signal system byalternating the polarity of each differential signal pair (e.g.alternating a differential pair for the analog signal and a differentialpair for the reference signal). Depending on the example, the polarityof the samples may be alternated between sampling and comparison by acomparator, as performed by chop switches 270 in SAR ADC 200. In otherexamples, the polarity of the samples are alternated by alternating apolarity of the analog signal prior to sampling by a capacitor array, asperformed by chop switches 370 in SAR ADC 300.

At block 503, a comparator in the SAR based ADC is employed to comparethe analog signal samples to reference values to generate digitalvalues. Such digital values may be determined according to successiveapproximation, by successively testing the analog signal verses variousreference values to measure the digital signal to a desired number ofbits.

At block 505, an un-chop switch is employed to demodulate the digitalvalues by selectively inverting the digital values. As noted above, thedigital values are selectively inverted/demodulated to cause the digitalvalues to maintain a constant polarity regardless of the position of thechop switches and un-chop switch(es). This allows the chopping to occurin a manner than is transparent to, and can be ignored by, othercomponents in the system. Depending on the example, the digital valuesmay be selectively inverted in a SAR register, as performed by SAR 230in SAR ADC 200. In other example, the digital values are selectivelyinverted between correction by correction circuit and processing by aDSP, as performed by un-chop switch 331 in SAR ADC 300.

At block 507, the modulated flicker noise is filtered out of the digitalvalues based on modulated flicker noise frequency. For example, when theanalog signal includes audio data, the polarity of the analog samplesmay be selectively alternated to increase a frequency of the flickernoise to a value outside an audio band. A bandpass filter in a DSP maythen filter out the flicker noise along with all other noise outside ofthe audio band.

Another mechanism, called auto-zero, may be employed to reduce flickernoise. Auto-zero may employ a comparator amplifier to drive a samplingcapacitor during a sampling phase, which causes flicker noise to besampled in the sampling capacitor. The sampled flicker noise thencancels flicker noise during the SAR phase. The disclosed chopperstabilized comparator system for SAR ADC may have many advantages overother flicker reduction and offset voltage reduction mechanisms, such asauto-zero. For example, the implementation disclosed herein may besimpler than other approaches and may only require the addition of someswitches, logic gates, and a controlling mechanism (e.g. SAR coresequencer) to generate a chop clock. This is vastly simpler to implementthan an auto-zero amplifier. Further, during input sampling, noauto-zero amplifier, which consumes power, is needed. Hence, thedisclosed mechanisms have a power consumption advantage over anauto-zero system. In addition, some chopper stabilization systems mayemploy both chop and un-chop switches in the analog domain. Thedisclosed methods/devices may utilize chop switches in the analog domainwith the un-chop operation operating in the digital domain. Hence, thepresent disclosure extends the chopping concept across mixed-signaldomains. Also, the present disclosure applies to applications where theband of interest is less than the Nyquist bandwidth of the ADC. This isuseful since the flicker noise is moved to a frequency for removal bysubsequent digital filtering. Hence the disclosed mechanisms areparticularly relevant to audio analog to digital converters where theADC conversion rate is many times higher than the 20 kHz audio band.Further, the disclosure applies directly to a SAR ADC architecture wherethe comparator is a dominant noise source. The disclosure provides anapproach to minimize comparator flicker noise with minimal additionalcircuitry and complexity. Finally, excluding an auto-zero amplifiercircuitry, allows the disclosed systems to reduce the die area of thecircuit which reduces integrated circuitry production costs.

Examples of the disclosure may operate on a particularly createdhardware, on firmware, digital signal processors, or on a speciallyprogrammed general purpose computer including a processor operatingaccording to programmed instructions. The terms “controller” or“processor” as used herein are intended to include microprocessors,microcomputers, Application Specific Integrated Circuits (ASICs), anddedicated hardware controllers. One or more aspects of the disclosuremay be embodied in computer-usable data and computer-executableinstructions (e.g. computer program products), such as in one or moreprogram modules, executed by one or more processors (includingmonitoring modules), or other devices. Generally, program modulesinclude routines, programs, objects, components, data structures, etc.that perform particular tasks or implement particular abstract datatypes when executed by a processor in a computer or other device. Thecomputer executable instructions may be stored on a non-transitorycomputer readable medium such as Random Access Memory (RAM), Read OnlyMemory (ROM), cache, Electrically Erasable Programmable Read-Only Memory(EEPROM), flash memory or other memory technology, Compact Disc ReadOnly Memory (CD-ROM), Digital Video Disc (DVD), or other optical diskstorage, magnetic cassettes, magnetic tape, magnetic disk storage orother magnetic storage devices, and any other volatile or nonvolatile,removable or non-removable media implemented in any technology. Computerreadable media excludes signals per se and transitory forms of signaltransmission. In addition, the functionality may be embodied in whole orin part in firmware or hardware equivalents such as integrated circuits,field programmable gate arrays (FPGA), and the like. Particular datastructures may be used to more effectively implement one or more aspectsof the disclosure, and such data structures are contemplated within thescope of computer executable instructions and computer-usable datadescribed herein.

Aspects of the present disclosure operate with various modifications andin alternative forms. Specific aspects have been shown by way of examplein the drawings and are described in detail herein below. However, itshould be noted that the examples disclosed herein are presented for thepurposes of clarity of discussion and are not intended to limit thescope of the general concepts disclosed to the specific examplesdescribed herein unless expressly limited. As such, the presentdisclosure is intended to cover all modifications, equivalents, andalternatives of the described aspects in light of the attached drawingsand claims.

References in the specification to embodiment, aspect, example, etc.,indicate that the described item may include a particular feature,structure, or characteristic. However, every disclosed aspect may or maynot necessarily include that particular feature, structure, orcharacteristic. Moreover, such phrases are not necessarily referring tothe same aspect unless specifically noted. Further, when a particularfeature, structure, or characteristic is described in connection with aparticular aspect, such feature, structure, or characteristic can beemployed in connection with another disclosed aspect whether or not suchfeature is explicitly described in conjunction with such other disclosedaspect.

Examples

Illustrative examples of the technologies disclosed herein are providedbelow. An embodiment of the technologies may include any one or more,and any combination of, the examples described below.

Example 1 includes an analog to digital converter (ADC) comprising: acomparator to compare sample values of an analog signal in an analogdomain to reference values to determine digital values in a digitaldomain, the digital values corresponding to the analog signal; one ormore chop switches to modulate the analog signal to increase a frequencyof flicker noise in the analog domain; and an un-chop switch todemodulate the digital values in the digital domain.

Example 2 includes the ADC of Example 1, further comprising a successiveapproximation register (SAR) to store digital value bits duringdetermination of the digital values, wherein the un-chop switch isimplemented in the SAR.

Example 3 includes the ADC of Example 1, further comprising: acorrection circuit to correct the digital values based on samplingcapacitor weights; and a digital signal processor (DSP) to process thedigital values, wherein the un-chop switch to demodulate the digitalvalues is coupled between the correction circuit and the DSP.

Example 4 includes the ADC of Examples 1-3, wherein the un-chop switchis a multiplexer coupled to an input line and an inverted line, theun-chop switch demodulating the digital values by switching an outputbetween the input line and the inverted line.

Example 5 includes the ADC of Examples 1-4, further comprising asuccessive approximation register (SAR) core sequencer to control thechop switches and the un-chop switch to align modulation in the analogdomain to demodulation in the digital domain to maintain consistentpolarity.

Example 6 includes the ADC of Examples 1-5, further comprising acapacitor array to store the sample values, wherein the chop switches tomodulate the analog signal are coupled to an input of the capacitorarray.

Example 7 includes the ADC of Examples 1-5, further comprising acapacitor array to store the sample values, wherein the chop switches tomodulate the analog signal are coupled between an output of thecapacitor array and an input to the comparator.

Example 8 includes the ADC of Examples 1-7, wherein the chop switchesincrease the frequency of the flicker noise to a value outside an audiofrequency band.

Example 9 includes the ADC of Examples 1-8, further comprising a digitalsignal processor to apply a digital filter to filter out the flickernoise by filtering out data associated with the increased flicker noisefrequency.

Example 10 includes a method comprising: selectively alternating apolarity of samples of an analog signal to modulate flicker noise;comparing, by a comparator in a Successive Approximation Register (SAR)based Analog to Digital Converter (ADC), the samples to reference valuesto generate digital values; demodulating the digital values byselectively inverting the digital values; and filtering the modulatedflicker noise out of the digital values based on modulated flicker noisefrequency.

Example 11 includes the method of Example 10, wherein the polarity ofthe samples are selectively alternated to increase a frequency of theflicker noise to a value outside an audio band.

Example 12 includes the method of Examples 10-11, wherein the polarityof the samples are alternated between sampling and comparison by thecomparator.

Example 13 includes the method of Examples 10-11, wherein the polarityof the samples are alternated by alternating a polarity of the analogsignal prior to sampling by a capacitor array.

Example 14 includes the method of Examples 10-13, wherein the digitalvalues are selectively inverted in a SAR register.

Example 154 includes the method of Examples 10-13, wherein the digitalvalues are selectively inverted between correction by correction circuitand processing by a digital signal processor (DSP).

Example 16 includes an analog to digital converter (ADC) comprising: aSuccessive Approximation Register (SAR) core sequencer configured to:employ chop switches to selectively alternate a polarity of samples ofan analog signal to modulate flicker noise prior to comparison toreference values by a SAR comparator to generate digital values; andemploy an un-chop switch to demodulate the digital values by selectivelyinverting the digital values to support filtering of the modulatedflicker noise out of the digital values based on modulated flicker noisefrequency.

Example 17 includes the ADC of Example 16, wherein the polarity of thesamples are alternated between sampling by a capacitor array andcomparison by the comparator.

Example 18 includes the ADC of Example 16, wherein the polarity of thesamples are alternated by alternating a polarity of the analog signalprior to sampling by a capacitor array.

Example 19 includes the ADC of Examples 16-18, wherein the digitalvalues are selectively inverted controlling a SAR register containingthe un-chop switch.

Example 20 includes the ADC of Examples 16-18, wherein the digitalvalues are selectively inverted after correction by a correctioncircuit.

The previously described examples of the disclosed subject matter havemany advantages that were either described or would be apparent to aperson of ordinary skill. Even so, all of these advantages or featuresare not required in all versions of the disclosed apparatus, systems, ormethods.

Additionally, this written description makes reference to particularfeatures. It is to be understood that the disclosure in thisspecification includes all possible combinations of those particularfeatures. Where a particular feature is disclosed in the context of aparticular aspect or example, that feature can also be used, to theextent possible, in the context of other aspects and examples.

Also, when reference is made in this application to a method having twoor more defined steps or operations, the defined steps or operations canbe carried out in any order or simultaneously, unless the contextexcludes those possibilities.

Although specific examples of the disclosure have been illustrated anddescribed for purposes of illustration, it will be understood thatvarious modifications may be made without departing from the spirit andscope of the disclosure. Accordingly, the disclosure should not belimited except as by the appended claims.

We claim:
 1. An analog to digital converter (ADC) comprising: acomparator to compare sample values of an analog signal in an analogdomain to reference values to determine digital values in a digitaldomain, the digital values corresponding to the analog signal; one ormore chop switches to modulate the analog signal to increase a frequencyof flicker noise in the analog domain; and an un-chop switch todemodulate the digital values in the digital domain.
 2. The ADC of claim1, further comprising a successive approximation register (SAR) to storedigital value bits during determination of the digital values, whereinthe un-chop switch is implemented in the SAR.
 3. The ADC of claim 1,further comprising: a correction circuit to correct the digital valuesbased on sampling capacitor weights; and a digital signal processor(DSP) to process the digital values, wherein the un-chop switch todemodulate the digital values is coupled between the correction circuitand the DSP.
 4. The ADC of claim 1, wherein the un-chop switch is amultiplexer coupled to an input line and an inverted line, the un-chopswitch demodulating the digital values by switching an output betweenthe input line and the inverted line.
 5. The ADC of claim 1, furthercomprising a successive approximation register (SAR) core sequencer tocontrol the chop switches and the un-chop switch to align modulation inthe analog domain to demodulation in the digital domain to maintainconsistent polarity.
 6. The ADC of claim 1, further comprising acapacitor array to store the sample values, wherein the chop switches tomodulate the analog signal are coupled to an input of the capacitorarray.
 7. The ADC of claim 1, further comprising a capacitor array tostore the sample values, wherein the chop switches to modulate theanalog signal are coupled between an output of the capacitor array andan input to the comparator.
 8. The ADC of claim 1, wherein the chopswitches increase the frequency of the flicker noise to a value outsidean audio frequency band.
 9. The ADC of claim 1, further comprising adigital signal processor to apply a digital filter to filter out theflicker noise by filtering out data associated with the increasedflicker noise frequency.
 10. A method comprising: selectivelyalternating a polarity of samples of an analog signal to modulateflicker noise; comparing, by a comparator in a Successive ApproximationRegister (SAR) based Analog to Digital Converter (ADC), the samples toreference values to generate digital values; demodulating the digitalvalues by selectively inverting the digital values; and filtering themodulated flicker noise out of the digital values based on modulatedflicker noise frequency.
 11. The method of claim 10, wherein thepolarity of the samples are selectively alternated to increase afrequency of the flicker noise to a value outside an audio band.
 12. Themethod of claim 10, wherein the polarity of the samples are alternatedbetween sampling and comparison by the comparator.
 13. The method ofclaim 10, wherein the polarity of the samples are alternated byalternating a polarity of the analog signal prior to sampling by acapacitor array.
 14. The method of claim 10, wherein the digital valuesare selectively inverted in a SAR register.
 15. The method of claim 10,wherein the digital values are selectively inverted between correctionby correction circuit and processing by a digital signal processor(DSP).
 16. A analog to digital converter (ADC) comprising: a SuccessiveApproximation Register (SAR) core sequencer configured to: employ chopswitches to selectively alternate a polarity of samples of an analogsignal to modulate flicker noise prior to comparison to reference valuesby a SAR comparator to generate digital values; and employ an un-chopswitch to demodulate the digital values by selectively inverting thedigital values to support filtering of the modulated flicker noise outof the digital values based on modulated flicker noise frequency. 17.The ADC of claim 16, wherein the polarity of the samples are alternatedbetween sampling by a capacitor array and comparison by the comparator.18. The ADC of claim 16, wherein the polarity of the samples arealternated by alternating a polarity of the analog signal prior tosampling by a capacitor array.
 19. The ADC of claim 16, wherein thedigital values are selectively inverted controlling a SAR registercontaining the un-chop switch.
 20. The ADC of claim 16, wherein thedigital values are selectively inverted after correction by a correctioncircuit.